Sitec had a requirement for an FPGA Engineer to join our client in Newport S/Wales. This is a contract position for a minimum period of 6 Months. The pay rate for this role is £DOE.
Due to a significant increase in expected key management contracts and the need to continue Ectocryp, R&D and MoL activities throughout 2018, there is a requirement for additional FPGA Engineer within the CyberSecurity development team.
* Must have experience of FPGA design & implementation for secure communications equipment or equivalent
* Must have excellent FPGA development process knowledge
* Must be an experienced engineer, fully versed in design methodologies for their field able to work on their own, but providing regular reporting
* Must have recent design experience of several of the following device families:
Must have recent experience of using several of the following tools/development environments:
* Altera Quartus II
* Mentor HDL Designer
* Mentor ModelSim
* MicroSemi Libero IDE
* Microsemi Libero SoC
* Xilinx Vivado
* Must be proficient in the use of VHDL
* Must be proficient in the use of at least one simulation tool
* Must be proficient in the use of at least one FPGA synthesis tool
* Must have a good understanding of requirements capture, and of work package definition and estimation
* Must be highly self-motivated, articulate, with good verbal and written communications skills
* Must have good team working skills
This vacancy is being advertised by Sitec.