Sitec has a requirement for an FPGA Engineer role working for our client based in Stevenage. This is a contract position for an estimated 6 months. The max rate of pay is up to £50 p/hr but DOE.
TASKS & ACCOUNTABILITIES
The FPGA Engineer will be required to perform complex design tasks within the communication processors group.
The role is based in Stevenage - there will be no shift work and no travel required.
Your main tasks and responsibilities will include:
* Decomposition of requirements into an architecture design and document the chosen design whilst describing any trade-offs performed.
* Detailed RTL design in VHDL.
* Verification of the RTL design and documenting the verification that was performed.
* Gate level implementation of the design including synthesis, placement and static timing analysis.
* Support integration of the FPGA into the target hardware.
* Ensure that all FPGA designs are developed in accordance with the company design process.
We are looking for candidates with the following skills and experience:
* Experienced in the complete design flow from requirements to design acceptance.
* Experienced in FPGA technologies and their tools including Xilinx ISE and Microsemi Libero.
* Experienced in VHDL simulation tools in particular Mentor Graphics Questa.
* Good analytical skills and methodical approach to problem resolution and investigations.
* Good communication skills and able to thrive in a team environment.
* Ability to present technical data in a clear and concise manner.
* Experience of the Linux operating system would be beneficial.
* Knowledge of scripting languages including TCL would be beneficial.
All candidates must be in a position to obtain UK security clearance to a minimum of BPSS level.
This vacancy is being advertised by Sitec.